1. Field of the Invention
This invention relates to the manufacture of semiconductor devices and more particularly to the formation of solid, dense electrically conductive paths through semiconductor bodies in order to reduce the number and length of conductive interconnections between logic and switching elements on a single body and/or between bodies in a multibody system.
2. Description of the Prior Art
Computer science has developed in an era of computer technology in which wire interconnects were inexpensive and logic and switching elements were expensive. Integrated circuit technology has recently reversed the cost situation leaving wire interconnects as the more expensive component. Interconnections between the integrated circuits of a single chip or wafer, whether made of wires or strips of conducting material, are expensive because they occupy most of the space on the wafer and cause most of the delay in electronic signals passing through the system. The same reasoning holds for interconnections between wafers. Computer architecture theory has just begun to take the cost reversal generated by integrated circuit technology into consideration. As a result, computer design has not yet taken advantage of the full range of capabilities implicit in microelectronics.
Current advances in computer design involve the development of a massively parallel information processing system for ultrahigh speed processing of multiple digital data streams. Such multiple data streams are encountered in situations where interactions of the physical data are significant as, for example, in image processing and studies of weather conditions, economics, hydrodynamics and stresses. The massively parallel array processor with many processors operating simultaneously and in parallel requires many interconnections between processors. With multiple processors, the number of interconnections, the space occupied by interconnections, the delay time caused by interconnections, the power consumed in interconnections, and the cost of interconnections has increased as the square of the number of processors in the system.
The massively parallel array processor system is built utilizing Complementary Metal Oxide Semiconductor/Silicon-on-Sapphire Large Scale Integration (CMOS/SOS LSI) circuitry. Processor arrays on many individual silicon-on-sapphire wafers must also be interconnected. In current technology, all such interconnections must run out to a pad on the edge of a wafer or chip. Such an interconnection scheme has several disadvantages.
First, the number of interconnection pads on the periphery of an LSI circuit is very limited. The relatively small number of interconnection pads severely restricts the information flow to and from an LSI circuit. For example, a typical memory chip has 16,384 bits arranged in a 128 by 128 array. An entire row of 128 bits can be assessed at one time, but a selector enables only a single bit to pass to an output pin. A typical memory system is made of 2,048 such chips arranged in 64 groups of 32. Only 32 chips can place their outputs on the 32 wires that join the bus to the central processor. Of the 262,144 bits that move less than a millimeter on each chip, only 2,048 move 3 millimeters to get off their chip and only 32 move a meter to the processor. In other words, because of an effective traffic tie-up on the interconnections, only about eight-thousandths of the available density of the memory chip can be used at present.
The second disadvantage of the interconnection scheme used by current technology is that a large fraction of the area of an LSI circuit is devoted to interconnections. This waste of a large area of a chip or a wafer is a direct consequence of the restriction of interconnections to substantially two-dimensional configurations. Previous methods of providing conventional conductive paths in three-dimensional configurations by placing the paths in layers on one chip have generally resulted in a decrease in the quality of the processed information due primarily to the phenomenon of cross-talk.